Leakage Reduction Using Power Gating Techniques in Sram Sense Amplifiers

Now-a-days leakage power is an important issue in microprocessor’s and hardware’s. In modern computer systems memory components covers 70 to 80 percent of total area of microprocessors that means memory contains more number of transistors. Generally leakage power dissipation proportional to the number of transistors. So the leakage power dissipation is more in the memories. In high performance memories systems sense amplifiers are very important part for sensing the output. In this paper we are focusing on memory leakage power reduction particularly in sense amplifiers using Fine Grain Power Gating (FGPG), Variable Body Biasing Technique (VBBT), Proposed Different Footer Dual Stack Technique (FDST) based both PMOS, one PMOS and one NMOS, both NMOS and Proposed PMOS Footer Triple Stack Technique (PFTST), PMOS Footer Four Stack technique (FFST) in Current Sense Amplifier (CSA), Charge Transfer Sense Amplifier (CTSA) and High Speed Sense Amplifier (HSSA).Variable Body Biasing Technique and PMOS Footer Triple Stack Technique are proposed techniques. We are applying these techniques in Different Sense Amplifiers. Proposed Variable body biasing leakage power dissipation in Current Sense Amplifier 1.5 times less than compare to Sleep Stack, Sleepy Keeper and 0.73 percent less than Forced Stack technique and this technique is much power efficient than other existing techniques. Second proposed Triple stack technique leakage power dissipation in Current sense amplifier is 2 to 3 times less than other techniques and total power dissipation almost 99 percent less than other existing techniques. Proposed techniques are also much efficient for other sense amplifiers.